1. Field of the Invention
Generally, the present disclosure relates to the manufacturing of sophisticated semiconductor devices, and, more specifically, to various methods of forming highly scaled semiconductor devices using a disposable spacer technique.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPU's, storage devices, ASIC's (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements in a given chip area according to a specified circuit layout, wherein field effect transistors (NMOS and PMOS transistors) represent one important type of circuit elements that substantially determine performance of the integrated circuits. During the fabrication of complex integrated circuits using, for instance, MOS technology, millions of transistors, e.g., NMOS transistors and/or PMOS transistors are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an NMOS transistor or a PMOS transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed between the highly doped regions source/drain regions.
In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin gate insulation layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends upon, among other things, the dopant concentration, the mobility of the charge carriers and, for a given extension of the channel region in the transistor width direction, the distance between the source and drain regions, which is also referred to as the channel length of the transistor. Hence, in combination with the capability of rapidly creating a conductive channel below the insulating layer upon application of the control voltage to the gate electrode, the conductivity of the channel region substantially affects the performance of MOS transistors. Thus, since the speed of creating the channel, which depends in part on the conductivity of the gate electrode, and the channel resistivity substantially determine the characteristics of the transistor, the scaling of the channel length, and associated therewith the reduction of channel resistivity, are dominant design efforts used to increase the operating speed of the integrated circuits.
The formation of transistors typically involves performing one or more ion implantation processes to form various doped regions in the substrate, such as halo implant regions, extension implant regions and deep source/drain implant regions. In many of the cases, one or more spacers are formed adjacent a gate electrode structure so as to control the location of the various implant regions. Typically, these spacers are made of silicon nitride to facilitate processing. More specifically, silicon nitride is often selected because it can be readily etched, and thus removed, relative to a silicon substrate and an underlying silicon dioxide liner layer which is frequently present to act as an etch stop layer when the silicon nitride spacer is removed. Although the use of multiple spacers in forming the various implant regions provides a mechanism whereby the location of various doped regions may be positioned so as to individually enhance the performance capabilities of the PMOS transistors and the NMOS transistors, the formation of so such spacers does have a downside. More specifically, during the formation of the various spacers, the exposed substrate, i.e., the areas of the substrate where the source/drain regions are to be formed, are also attacked which leads to undesirable localized recessing of the substrate in those areas. In some application, such recessing may remove about 20-40 nm of the substrate 10. Such recessing may, in effect, consume some of the implanted dopant materials in the substrate 10. Such recessing may result in increased parasitic resistance which may reduce the drive current of the transistors. Such recessing may also effectively increase the distance current must travel through the transistor, which may tend to reduce the operating speed of the transistors.
Another problem arises because the space between adjacent gate electrode structures, or more precisely, between the sidewall spacers formed on adjacent gate electrode structures is very small. For example, the current-day transistors may have a gate length of about 25-30 nm, and such transistors may be formed with a gate pitch that ranges from about 160-190 nm, depending upon the particular application. Thus, the distance between adjacent gate structures may be about 130-160 nm. The lateral space between adjacent gate structures is also typically occupied by a conformal liner layer and one or more spacers that are used in the various implantation processes described above. Thus, the lateral space between adjacent spacers will be even smaller.
Device designers are under constant pressure to increase the operating speed and electrical performance of transistors and integrated circuit products that employ such transistors. Given that the gate length (the distance between the source and drain regions) on modern transistor devices may be approximately 30-50 nm, and that further scaling is anticipated in the future, device designers have employed a variety of techniques in an effort to improve device performance, e.g., the use of high-k dielectrics, the use metal gate electrode structures, the incorporation of work function metals in the gate electrode structure and the use of channel stress engineering techniques on transistors (create a tensile stress in the channel region for NMOS transistors and create a compressive stress in the channel region for PMOS transistors). Stress engineering techniques typically involve the formation of specifically made silicon nitride layers that are selectively formed above appropriate transistors, i.e., a layer of silicon nitride that is intended to impart a tensile stress in the channel region of a NMOS transistor would only be formed above the NMOS transistors. Such selective formation may be accomplished by masking the PMOS transistors and then blanket depositing the layer of silicon nitride, or by initially blanket depositing the layer of silicon nitride across the entire substrate and then performing an etching process to selectively remove the silicon nitride from above the PMOS transistors. Conversely, for PMOS transistors, a layer of silicon nitride that is intended to impart a compressive stress in the channel region of a PMOS transistor is formed above the PMOS transistors. The techniques employed in forming such nitride layers with the desired tensile or compressive stress are well known to those skilled in the art.
However, as noted above, the lateral dimension between adjacent spacers is so small that it makes the formation of such stress-inducing layers very difficult. More specifically, in forming such stress-inducing material layers, even if a highly conformal deposition process is used to form these layers, the stress-inducing layers do not completely fill the lateral space between the adjacent spacers. This may result in the formation of undesirable voids in such layers. In a later process step whereby conductive contacts are formed to the substrate, these voids may become wholly or partially filled with conductive material, which constitute defects that can lead to potential short circuit problems. As an example, such defects may provide a short circuit between adjacent conductive contacts and/or adjacent gate structures. Such defects may cause a decrease in the electrical performance capability of the device or, in a worst-case scenario, complete device failure. In some cases, the filled voids may be referred to as so-called tungsten subways.
The present disclosure is directed to various methods that may avoid, or at least reduce, the effects of one or more of the problems identified above.